1. Field
This invention relates to phase locked loops (PLLs), and more specifically to improving PLL jitter performance and stability.
2. Background
Phase locked loops (PLLs) are commonly used for microprocessor clock generation. As the frequency of the PLL is increased to allow the microprocessor to run faster, the loop dynamics of the PLL varies and PLL stability becomes an issue. These PLL loop dynamics relate to the PLL damping factor and natural frequency. As the output frequency of the PLL increases and the loop dynamics of the PLL vary, this results in increased jitter at the output clock of the PLL.
Equation 1 shows a relationship of damping factor to loop filter resistance, where y is the ratio of loop filter resistance to the VCO (voltage controlled oscillator) VCR (voltage controlled resistance) and N is the core PLL frequency multiplier value. These are not all of the parameters that factor into the damping factor.                               Damping          ⁢                                    xe2x80x83                        ⁢                          xe2x80x83                                ⁢          factor          ⁢                      xe2x80x83                    ⁢          ζ                ∝                  y                      N                                              (        1        )            
A damping factor represents how stable a system is. As shown in Eq. 1, the damping factor is proportional to the ratio loop filter resistance of the PLL over the square root of a multiplier value of the PLL. Therefore, as the range of frequencies from the PLL varies, the multiplier value varies, therefore, affecting the damping factor.
For example, if the PLL supplies a core clock of 1 GHz and 6 GHz, from an input frequency of 100 MHz, a multiplier value of 10 and a multiplier value of 60 may be used, respectively. Plugging these into Eq. 1 shows that the damping factor will experience a large variation causing jitter that may be hard to tolerate in the system.
Equation 2 shows a relationship of the natural frequency to input clock frequency and charge pump current. The natural frequency is shown as xcfx89N and xcfx89input is the PLL input frequency. Another relationship regarding the damping factor is shown in equation 3.                              Natural          ⁢                      xe2x80x83                    ⁢          frequency          ⁢                      xe2x80x83                    ⁢                      ω            N                          ∝                              ω            input                    ⁢                                                    x                1                            ⁢              N                                                          (        2        )                                          Damping          ⁢                                    xe2x80x83                        ⁢                          xe2x80x83                                ⁢          factor          ⁢                      xe2x80x83                    ⁢          ζ                ∝                              x            2                                                              x                1                            ⁢              N                                                          (        3        )            
As the frequency of the PLL increases, generally the input frequency to the PLL increases. As shown in Eq. 2, the natural frequency of the PLL is proportional to the input frequency multiplied by the square root of a ratio x1 multiplied by the PLL frequency multiplier value N. The ratio, x1, is a ratio of the charge pump current in a first charge pump to the VCO tail current. The parameter x2 is a ratio of the charge pump current in a second charge pump to the VCO tail current. As shown in Eq. 3, both the ratio x1 and the ratio x2 affect the damping factor since the damping factor is proportional to x2 divided by the square root of x1 multiplied by N. Therefore, as can be seen from Eq. 2, as the input frequency increases, the natural frequency increases. As the natural frequency increases, the amount of jitter at the input to the PLL increases. This jitter at the input of the PLL may be magnified through the PLL where it then shows up on the output core clock of the PLL.
Currently, a cascaded PLL approach is used to reduce damping factor variation. The input clock for the core PLL is the output clock of a previous PLL. Frequency multipliers that receive the first PLL output clock reside between the first PLL and the core PLL. Any one of the outputs of the multipliers may be selected to be the input clock to the core PLL. This makes it possible to change core PLL input clock frequency according to the multiplier value needed for the core PLL output clock frequencies. Therefore, the frequency multiplier value N for the core PLL can be set to vary less (for a given range of frequencies), meaning its damping factor will vary less.
However, cascaded PLLs are problematic in that the bandwidths for the two PLLs have to be separated big enough so that jitters are not amplified twice. This limits PLL design flexibility and optimization. Moreover, a cascaded PLL approach does not address the issue of large natural frequency variation. Further, a cascaded PLL approach requires two PLLs, therefore, requiring more space and other resource requirements.